This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-272304, filed Sep. 27, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a method of manufacturing a semiconductor device, particularly, to a method of making a gate wiring layer of a semiconductor device.
In making a gate wiring layer on a semiconductor substrate, it has been carried out to pattern a film of a gate wiring material by dry etching.
FIG. 5D is a cross sectional view showing a semiconductor substrate having a gate wiring layer. As shown in the drawing, an insulating layer 102 of, for example, a silicon oxide film (SiO2) is provided on a semiconductor substrate 101 such as a silicon substrate, and a gate wiring layer 103 is formed on the surface of the insulating film 102. The gate wiring layer 103 is electrically connected to a capacitor formed in the semiconductor substrate 101 or a metal wiring layer (not shown) on the silicon semiconductor substrate 101. An insulating spacer 106 of, for example, a silicon nitride (Si3N4) layer is provided on the side wall of the gate wiring layer 103, and an insulating layer 107 of, for example, a silicon oxide (SiO2) layer is provided to cover the gate wiring layer 103. The gate wiring layer 103 is formed of a material such as silicon, polycrystalline silicon (polysilicon), or tungsten, or a stacked layer of these materials.
The method of making the conventional gate wiring layer will now be described with reference to FIGS. 5A to 5D. In the first step, formed successively on a semiconductor substrate 101 are a gate insulating layer 102, a conductive layer of a gate wiring layer 103, and an antireflection layer 104 for preventing the reflected light from acting on a photoresist layer, as shown in FIG. 5A. The antireflection layer 104 is composed of an organic compound. Then, a photoresist layer 105 is formed on the antireflection layer 104 and patterned by a lithography technique so as to have a configuration similar to that of the gate wiring layer, as shown in FIG. 5B. Then, using the patterned photoresist layer 105 as a mask, the antireflection layer 104 and the conductive layer are etched by dry etching to provide a gate wiring layer 103 having a predetermined pattern. After removing the photoresist layer 105 and the antireflection layer 104, an insulating layer 106 is deposited over the substrate surface as shown in FIG. 5C. Further, the insulating layer 106 is etched back by the dry etching to provide an insulating spacer 106 at the side wall of the gate wiring layer 103, followed by depositing an insulating layer 107 to cover the gate wiring 103 therewith, as shown in FIG. 5D.
When the conductive layer of the gate wiring layer 103 provided over the semiconductor substrate 101 is etched by using the photoresist layer 105 used as the mask, the etching treatment must be stopped so that the gate insulating layer 102 on the semiconductor substrate 101 is unremoved. In the case of under-etching as shown in FIG. 6A, a trailing configuration may be caused between the gate wiring layers, or sufficient etching may not be carried out to provide an electrical short-circuiting in the gate wiring layers. Also, in the case of over-etching as shown in FIG. 6B, the gate insulating layer 102 may be etched by a halogen-gas such as HBr or Cl2, which are contained in the etching gas used for selectively etching the conductive layer of the gate wiring layers, and the semiconductor substrate 101 may also be etched. In recent years, the gate insulating layer will be made thinner and thinner in order to increase the operating speed of the MOS transistor. As a result, it will be difficult to control the etching process of the conductive layer of the gate wiring layers without removing the gate insulating layer over the entire surface of the semiconductor substrate.
Further, the gate insulating layer interposed between the semiconductor substrate and the gate wiring layers will be subjected to plasma damage by selective etching of the conductive layer and by deposition of an insulating layer using plasma CVD (Chemical Vapor Deposition).
An object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which permits selectively stopping the etching treatment not to etch the gate insulating layer.
Another object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which utilizes a carbon-based layer.
Still another object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which utilizes a carbon-based layer for preventing the gate insulating layer and the semiconductor substrate from being etched.
The present invention is directed to a method of making a gate wiring layer on a semiconductor substrate and comprises the step of forming an insulating layer of, for example, SiO2 on a semiconductor substrate, the step of forming a carbon-based layer, the step of forming a predetermined mask on the carbon-based layer, and the step of patterning the carbon-based layer. It should be noted that the carbon-based layer is subjected to dry etching using an oxygen gas, a carbon monoxide gas or a mixed gas containing an oxygen gas, a nitrogen gas, a carbon monoxide gas and an argon gas and not containing halogen such that the etching is selectively stopped before the insulating layer is etched.
The insulating layer of, for example, SiO2 is etched by the dry etching using a gas containing halogen such as F and Cl. However, the reactive etching does not almost proceeds, by the dry etching using a gas of oxygen, nitrogen, carbon monoxide or argon, the gas not containing the halogen, or a mixed gas thereof.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming an insulating layer on a semiconductor substrate; forming a carbon-based layer on the insulating layer; forming a mask of a predetermined pattern on the carbon-based layer; etching the carbon-based layer with a gas containing oxygen by using the mask, thereby providing an opening therein; burying a conductive material within the opening of the carbon-based layer after removing the mask therefrom; and removing the carbon-based layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating layer on a semiconductor substrate; forming a carbon-based layer on the first insulating layer; forming a mask having a predetermined pattern on the carbon-based layer; etching the carbon-based layer with an oxygen-containing gas to form a predetermined pattern; removing the mask and forming a second insulating layer on the first insulating layer in a manner to bury the patterned carbon-based layer; removing the carbon-based layer to form an opening in the second insulating layer; and burying a conductive material in the opening.
In this case, after the insulating layer at the bottom of the opening is removed, an insulating layer corresponding to the gate insulating layer may be formed at the bottom.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating layer on a semiconductor substrate; forming a carbon-based layer on the first insulating layer; forming a second insulating layer on the carbon-based layer; forming a mask having a predetermined pattern on the second insulating layer; selectively removing the second insulating film by using the mask to expose the carbon-based layer; selectively etching the exposed carbon-based layer with an oxygen-containing gas to provide an opening in the carbon-based layer; burying a conductive material in the opening of the carbon-based layer; and removing the carbon-based layer.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating layer on a semiconductor substrate; forming a carbon-based layer on the first insulating film; forming a second insulating layer on the carbon-based layer; forming a mask having a predetermined pattern on the second insulating layer; selectively removing the second insulating layer by using the mask; etching the carbon-based layer with an oxygen-containing gas by using the mask to provide a predetermined pattern; removing the mask and subsequently forming a third insulating layer on the second insulating layer to bury the patterned carbon-based layer; removing the carbon-based layer to provide an opening in the third insulating layer; and burying a conductive material in the opening of the third insulating layer.
Using a photoresist material as the mask, an organic silicon oxide layer may be interposed between the photoresist layer and the carbon-based layer. The etching gas does not contain a halogen gas and is composed of a mixed gas of an oxygen gas and a carbon monoxide gas or a mixed gas of an oxygen gas, a nitrogen gas, a carbon monoxide gas and an argon gas.
As the gate insulating layer, a single layer of silicon, polysilicon or tungsten, or a stacked layer of these materials may be employed. The thickness of the first insulating layer may be defined by 10 nm or less.
As materials of the carbon-based layer, novolak resin, polyvinylphenol, polymethacrylate, polyarylene, polyaryleneether, or polyimide and the like can be used in addition to a carbon layer. Since the carbon-based layer is subjected to a heat treatment such as a diffusion process, it is desirable for the carbon-based layer to be formed of, particularly, a material having a high heat resistance. Therefore, it is preferable to use polyarylene, polyaryleneether or polyimide.
Since it is difficult to dissolve these organic materials in a solvent, it is desirable to prepare solution materials. According to the necessity, a thermal polymerization inhibitor for improving the storage stability, an adhesion strength improving agent for improving the adhesion strength to the layer to be processed, a conductive material, a material for generating conductivity by light or heat, and a surface active agent for improving the coating properties may be added to the solvent. As the solvents, which are not particularly limited in the present invention, given are for example, ketone series solvents such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexane; cellosolve series solvents such as methylcellosolve, methylcellosolve acetate, and ethylcellosolve; ester series solvents such as ethyl lactate, ethyl acetate, butyl acetate, and isoamyl acetate; alcohol series solvents such as methanol, ethanol, and isopropanol; as well as anisol, toluene, xylene, naphtha and water.
As described above, a masking solution is prepared. After a substrate is coated with the masking solution by, for example, spin coating, it is heated to evaporate the masking solution, thereby providing a masking layer thereupon. The heating temperature, which is not particularly limited in the present invention, may be in a range of 100xc2x0 C.-500xc2x0 C. If the heating temperature is lower than 100xc2x0 C., it is difficult to dry the solvent as desired. However, if the heating temperature exceeds 500xc2x0 C., it is possible for the processed layer to be denatured.
The carbon-based layer may be formed by, for example, a sputtering technique, a CVD technique, or a coating technique in which the substrate is coated with a material dissolved in a solvent, followed by applying a heat treatment to the substrate.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.